Table of Contents
VHDL IMPLEMENTATION OF A HIGH-SPEED SYMMETRIC CROSSBAR SWITCH
Road map
Network switch
Packet switches
ATM packet
Switch architecture
Crossbar architecture
Buffering in switches
Input queuing (IQ)
How to remove HOL blocking?
Multiple queues at inputs
DAMQ buffers
Road map
Our switch design
Overall view of the switch
Input port module (voq_input)
Input port module (voq_input)
Input port module
Buffer
Virtual dynamic queues
Virtual dynamic queues (example)
Virtual dynamic queues
Input port module
Look up table (LUT)
Initialized ROM
Input port module
Write sequence controller
VCI controller
Read sequence controller
Linked list update controller
Initializing the linked lists
Update linked lists after write operation
Update linked lists after write operation
Update linked lists after packet is read
Update linked lists after packet is read
Road map
Scheduler (voq_c_bar)
Two-dimensional propagation arbiter
Diagonal propagation arbiter
Diagonal propagation arbiter (DPA)
Road map
Fabric module (voq_fabric)
Fabric module
Fabric module
Fabric module (example)
Device summary
Simulation results
Simulation results
Concluding remarks: history
Concluding remarks
Future work
References
Output queuing (OQ)
Registers associated with buffer
Fabric module (example)
Simulation results
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