----------------------------------------------------------------------------
-- Fpga LCD Code                                                          --
----------------------------------------------------------------------------
-- Author: 	 Veljko Jovanovic                                             --
-- Date: 	 February 8th, 2000										  	  --  
-- Version:  2.1 (created from fpga_base.vhd Version 2.0)                 --
-- Filename: fpga_lcd.vhd											 	  --
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE	ieee.std_logic_unsigned.all;

ENTITY fpga_lcd IS				 -- Structural description of input/output of box.
        PORT
        (
        	clk 	: in bit;  							-- 10 KHz internal clock.
            eclk    : in bit; 							-- 8 MHz clock from the HC12
			sclk	: in bit; 							-- 2 Hz internal clock.

            led   	: out std_logic;   					-- LED.
            irqz    	: out std_logic;				-- IRQ indicator.
            xirqz   	: out std_logic;				-- non-mask. IRQ indicator.

			pa		: in std_logic_vector(2 downto 0); 	-- LCD Instructions.
            lcde  	: out std_logic; 					-- LCD enable signal.
			lcdrw 	: out std_logic; 					-- LCD Read/Write signal.
			lcdrs 	: out std_logic; 					-- LCD RS control line.

            pb    	: in std_logic_vector(7 downto 0); -- LCD Data from HC12.
            lcd   	: out std_logic_vector(7 downto 0) -- LCD Data to LCD.
        );
END fpga_lcd;

ARCHITECTURE behaviour OF fpga_lcd IS
BEGIN
--*******************************************************************************
LedLogic : process					-- always executed.
begin								-- LED blinks at a 2Hz rate.
  if (sclk = '1') then
    led <= '1';						-- led off.
  else
    led <= '0';						-- led on.
  end if;
end process LedLogic;
--*******************************************************************************
-- Main Code
--*******************************************************************************
  lcd <= pb;                              		-- PortB => LCD Data. 
  lcdrs <= pa(0);                         		-- LCD register select. 
  lcdrw <= pa(1);                         		-- LCD read/write. 
  lcde  <= pa(2);                         	 	-- LCD enable.  
  xirqz  <= '1';								-- disable XIRQ.
  irqz <= '1';									-- disable IRQ.
--*******************************************************************************
END behaviour;