----------------------------------------------------------------------------
-- Fpga TONE Code                                                          --
----------------------------------------------------------------------------
-- Author: 	 Veljko Jovanovic                                             --
-- Date: 	 February 8th, 2000										  	  --  
-- Version:  2.2 (created from fpga_base.vhd Version 2.1)                 --
-- Filename: fpga_irq.vhd											 	  --
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE	ieee.std_logic_unsigned.all;

ENTITY fpga_tone IS				 -- Structural description of input/output of box.
        PORT
        (
        	clk 	: in std_logic;  							-- 10 KHz internal clock.
            eclk    : in std_logic; 							-- 8 MHz clock from the HC12 (PE[4]).
			sclk	: in std_logic; 							-- 2 Hz internal clock.

            led   	: out std_logic;   					-- LED.
            irqz    : out std_logic;					-- IRQ indicator (PE[1]).
            xirqz   : out std_logic;					-- non-mask. IRQ indicator (PE[0]).

			pa		: in std_logic_vector(2 downto 0); 	-- LCD Instructions (PA[2..0]).
            lcde  	: out std_logic; 					-- LCD enable signal.
			lcdrw 	: out std_logic; 					-- LCD Read/Write signal.
			lcdrs 	: out std_logic; 					-- LCD RS control line.

            pb    	: in std_logic_vector(7 downto 0); 	-- LCD Data from HC12 (PB[7..0]).
            lcd   	: out std_logic_vector(7 downto 0);	-- LCD Data to LCD.

            buttons	: in std_logic_vector(3 downto 0);	-- Switches 4 downto 1.
            code 	: out std_logic_vector(3 downto 0); 	-- Switches to HC12 (PA[7..4]).	               
			headleft: inout std_logic;					-- Left Headphone
			headright: inout std_logic					-- Right Headphone
        );
END fpga_tone;

ARCHITECTURE behaviour OF fpga_tone IS

signal count : STD_LOGIC_VECTOR(6 DOWNTO 0);

BEGIN

--*******************************************************************************
-- Main code
--*******************************************************************************
  lcd <= pb;                              		-- PortB => LCD Data. 
  lcdrs <= pa(0);                         		-- LCD register select. 
  lcdrw <= pa(1);                         		-- LCD read/write. 
  lcde  <= pa(2);                         	 	-- LCD enable.  

  code <= buttons;								-- Switches to PortA[7..4]

  xirqz  <= '1';								-- disable XIRQ.

  led <= '1';
  irqz <= '1';

--*******************************************************************************
sound: process(clk)
 begin
 	if (clk'event and clk = '1') then			-- On positive clock edge
        if count = "1000000" then					-- If half tone period
 	       headleft <= NOT(headleft);								-- Toggle headphone signal
 	       headright <= NOT(headright);
           count <= "0000000";
		else
		   count <= count + 1;						-- Other increase count
		end if;
 	end if;
end process;

END behaviour;