----------------------------------------------------------------------------
-- Fpga Tone Code                                                         --
----------------------------------------------------------------------------
-- Author: 	 Veljko Jovanovic                                             --
-- Date: 	 February 25th, 2000									  	  --  
-- Version:  2.3 (created from fpga_irq.vhd Version 2.2)                  --
-- Filename: fpga_tone.vhd											 	  --
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE	ieee.std_logic_unsigned.all;

ENTITY fpga_tone IS				 -- Structural description of input/output of box.
        PORT
        (
        	clk 	: in bit;  							-- 8 MHz clock on pin 2.
            eclk    : in bit; 							-- 8 MHz clock from the HC12 (PE[4]).
			sclk	: in bit; 							-- 2 Hz internal clock.

            led   	: out std_logic;   					-- LED.
            irqz    : out std_logic;					-- IRQ indicator (PE[1]).
            xirqz   : out std_logic;					-- non-mask. IRQ indicator (PE[0]).

			pa		: in std_logic_vector(2 downto 0); 	-- LCD Instructions (PA[2..0]).
            lcde  	: out std_logic; 					-- LCD enable signal.
			lcdrw 	: out std_logic; 					-- LCD Read/Write signal.
			lcdrs 	: out std_logic; 					-- LCD RS control line.

            pb    	: in std_logic_vector(7 downto 0); 	-- LCD Data from HC12 (PB[7..0]).
            lcd   	: out std_logic_vector(7 downto 0);	-- LCD Data to LCD.

            buttons	: in std_logic_vector(3 downto 0);	-- Switches 4 downto 1.
            code 	: out std_logic_vector(3 downto 0); -- Switches to HC12 (PA[7..4]).

            LeftHp	: out std_logic;					-- Left Headphone
			RightHp	: out std_logic 					-- Right Headphone
        );
END fpga_tone;

ARCHITECTURE behaviour OF fpga_tone IS

  -- Counter used to divide the 8MHz clock frequency to get the desired tones
  --
  signal count : std_logic_vector(12 downto 0) := "0000000000000";

BEGIN
--*******************************************************************************
LedLogic : process					-- always executed
begin								-- LED blinks at a 2Hz rate unless a button is pressed
  if (sclk = '1' and buttons="1111") then 				
    led <= '1';						-- led off.
  else
    led <= '0';						-- led on.
  end if;
end process LedLogic;
--*******************************************************************************
interrupt: process(buttons) 				-- executed when buttons change.
begin                                     	-- set IRQ and LED.
	if ((buttons(0)='0') or (buttons(1)='0') or (buttons(2)='0') or (buttons(3)='0')) then
	  irqz <= '0';						-- IRQ set.
    else
      irqz <= '1';						-- IRQ clear.
    end if;
end process interrupt;
--*******************************************************************************
sound: process(clk)		    		-- executed when clk changes to output sound.
begin
	if (clk'event and clk='1') then			-- positive clock edge.
      -- C6 (1046.5 Hz)
	  if count="0111011101110" then 	    -- half sound wave.
		LeftHp <= '1';
		RightHp <= '1';
		count <= count + 1;
	  elsif count = "1110111011100" then	-- full sound wave.
		LeftHp <= '0';
		RightHp <= '0';
		count <= "0000000000000";			-- reset counter.
	  else
		count <= count + 1;					-- increment counter.
 	  end if;

	end if;
end process sound;
--*******************************************************************************
-- Main code
--*******************************************************************************
  lcd <= pb;                              		-- PortB => LCD Data. 
  lcdrs <= pa(0);                         		-- LCD register select. 
  lcdrw <= pa(1);                         		-- LCD read/write. 
  lcde  <= pa(2);                         	 	-- LCD enable.  

  code <= buttons;								-- Switches to PortA[7..4]

  xirqz  <= '1';								-- disable XIRQ.
--*******************************************************************************
END behaviour;