Parameterized Counter Megafunction Altera recommends using the lpm_counter function instead of any other type of binary counter, including old-style counter macrofunctions. AHDL Function Prototype: FUNCTION lpm_counter (data[LPM_WIDTH-1..0], clock, clk_en, cnt_en, updown, aclr, aset, aconst, aload, sclr, sset, sconst, sload) WITH (LPM_WIDTH, LPM_DIRECTION, LPM_MODULUS, LPM_AVALUE, LPM_SVALUE) RETURNS (q[LPM_WIDTH-1..0], eq[15..0]); The sconst and aconst ports are provided only for backward compatibility with MAX+PLUS II version 6.0 designs and LPM 2.0.1. VHDL Component Declaration: COMPONENT lpm_counter GENERIC (LPM_WIDTH: POSITIVE; LPM_MODULUS: STRING := "UNUSED"; LPM_AVALUE: STRING := "UNUSED"; LPM_SVALUE: STRING := "UNUSED"; LPM_DIRECTION: STRING := "UNUSED"; LPM_TYPE: STRING := L_COUNTER; LPM_PVALUE: STRING := "UNUSED"; LPM_HINT : STRING := "UNUSED"); PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); clock: IN STD_LOGIC; clk_en: IN STD_LOGIC := '1'; cnt_en: IN STD_LOGIC := '1'; updown: IN STD_LOGIC := '1'; sload: IN STD_LOGIC := '0'; sset: IN STD_LOGIC := '0'; sclr: IN STD_LOGIC := '0'; aload: IN STD_LOGIC := '0'; aset: IN STD_LOGIC := '0'; aclr: IN STD_LOGIC := '0'; eq: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)); END COMPONENT; Ports: INPUTS Port Name Required Description Comments data[] No Parallel data input to the counter. Input port LPM_WIDTH wide. Uses aload and/or sload. clock Yes Positive-edge-triggered Clock. clk_en No Clock Enable input. Enables all synchronous activities. Default = 1. cnt_en No Count Enable input. Disables count when low (0) without affecting sload, sset, or sclr. Default = 1. updown No Controls the direction of the count. High (1) = count up. Low (0) = count down. Default = up (1). If the LPM_DIRECTION parameter is used, the updown port cannot be connected. If LPM_DIRECTION is not used, the updown port is optional. aclr No Asynchronous Clear input. Default = 0. If both aset and aclr are used and both are asserted, aclr is dominant. For outputs such as q[] and eq[], aclr affects the output before polarity is applied. aset No Asynchronous set input. Default = 0. Sets q[] outputs to all 1's, or to the value specified by LPM_AVALUE. If both aset and aclr are used and both are asserted, aclr is dominant. For outputs such as q[] and eq[], aset affects the output before polarity is applied. aload No Asynchronous load input. Asynchronously loads the counter with the value on the data input. Default = 0. If aload is used, data[] must be used. sclr No Synchronous Clear input. Clears the counter on the next active Clock edge. Default = 0. If both sset and sclr are used and both are asserted, sclr is dominant. For outputs such as q[] and eq[], sclr affects the output before polarity is applied. sset No Synchronous set input. Sets the counter on the next active Clock edge. Default = 0. Sets q outputs to all 1's, or to the value specified by LPM_SVALUE. If both sset and sclr are used and both are asserted, sclr is dominant. For outputs such as q[] and eq[], sset affects the output before polarity is applied. sload No Synchronous load input. Loads the counter with data[] on the next active Clock edge. Default = 0. If sload is used, data must be connected. OUTPUTS Port Name Required Description Comments q[] No Data output from the counter. Output port LPM_WIDTH wide. Either q[] or at least one of the eq[] ports must be connected. eq[] No Counter decode output. Active-high when the counter reaches the specified count value. Either the q[] port or eq[] port must be connected. Up to c eq ports can be used (c <=15). Only the 16 lowest count values are decoded. When the count value is c, the eqc output is set high (1). For example, when the count is 0, eq0 = 1; when the count is 1, eq1 = 1; and when the count is 15, eq15 = 1. Decoded outputs for count values of 16 or greater require external decoding. The eq[] outputs are asynchronous. Parameters: Parameter Type Required Description LPM_WIDTH Integer Yes Width of the data[], q[], and eq[] ports. If no output ports are specified, the value is the number of bits in the count. LPM_DIRECTION String No Values are "UP" and "DOWN". If the LPM_DIRECTION parameter is used, the updown port cannot be connected. When the updown port is not connected, the default for the LPM_DIRECTION parameter is "UP". LPM_MODULUS Integer No The maximum count, plus one. Number of unique states in the counter's cycle. If the load value is larger than the LPM_MODULUS parameter, the behavior of the counter is not specified. LPM_AVALUE Integer No Constant value that is loaded when aset is high. Must be used if aconst is used. If the value specified is larger than , the behavior of the counter is an undefined (X) logic level, where is LPM_MODULUS, if present, or 2 ^ LPM_WIDTH. LPM_SVALUE Integer No Constant value that is loaded on the rising edge of clock when sconst is high. Must be used if sconst is used. Function: Inputs | Outputs | Function aclr aload clock sset cnt_en | | aset clk_en sclr sload updown | q[LPM_WIDTH-1..0] | 1 X X X X X X X X X | 000... | 0 1 X X X X X X X X | 111... | 0 1 X X X X X X X X | LPM_AVALUE | Asynchronous set to value | | specified for LPM_AVALUE 0 0 1 X X X X X X X | data[LPM_WIDTH-1..0] | Asynchronous load from | | data[] input 0 0 0 0 X X X X X X | q[LPM_WIDTH-1..0] | Hold current count value 0 0 0 1 1 X X X X | 000... | Synchronous Clear 0 0 0 1 0 1 X X X | 111... | Synchronous set 0 0 0 1 X 1 1 X X | LPM_SVALUE | Synchronous set to value | | specified for LPM_SVALUE 0 0 0 1 0 0 0 0 0 | q[LPM_WIDTH-1..0] | Hold current count value 0 0 0 1 0 0 0 X X | data[LPM_WIDTH-1..0] | Synchronous load from | | data[] input 0 0 0 1 0 0 0 1 1 | q[LPM_WIDTH-1..0]+1 | Count up 0 0 0 1 0 0 0 1 0 | q[LPM_WIDTH-1..0]-1 | Count down Typical Implementation: The lpm_counter function offers four different modes that allow you to force the count value to a specific number. You can use each of the modes either synchronously (port names starting with an "s") or asynchronously (port names starting with an "a"). Mode Description Setting (forcing to all 1's) Asserting the sset or aset signal forces the count value to all 1's. Clearing (setting to all 0's) Asserting the sclr or aclr pin forces the count value to all 0's. Loading (from data bus) Asserting the aload or sload signal loads the count value from the data input. Loading (to a predetermined value) Asserting the sset or aset signal loads the count value to the number specified by the LPM_SVALUE or LPM_AVALUE parameter, respectively. Resource Usage: The following table summarizes the resource usage for an lpm_counter function used to implement a 16-bit counter with an up/down control, a count enable input, a synchronous load input, and an asynchronous Clear input. Logic cell usage scales linearly in proportion to counter width. Design Goals | Design Results Device Family Optimization | Width Logic Cells Speed (MHz) Notes FLEX 8000, FLEX 10K Routability | 16 45 29 MHz Note (1) Speed | 16 17 112 MHz Note (1) | MAX 5000, MAX 7000, and MAX 9000 Routability | 16 16 125 MHz Note (2) See also: Megafunctions/LPM