Folder content

Spring 2000
ENSC 151
DIGITAL AND COMPUTER DESIGN LABORATORY

FOLDER CONTENT:

GENERAL INFO

LECTURE SLIDES:

EVB floor plan: HC12 and ALTERA chip interconnections.
Form Fred Heep's lecture: how to protect your EVB boards when interfacing it to the outside world.
HC12 basic info and the programming model.
Addressing modes and AS11 Assembler (20 little examples).
On interrupts and real-time events.
Examples of a finite state machine (FSM): Design of a traffic model and a leaky bucket algorithm.
MOS transistor: silicon implementation, logic gates (inverter, AND, OR), transistor layout, and PLA (AND/OR plane).
Design example: FIFO (concepts, logic, layout, floor plan).
Design example: 4 and 12 bit counters (state diagrams, logic functions, implementation with standard cells, delay optimization).
Design and VHDL examples: 2 bit counter, half adder, odd and even parity checkers.
More VHDL examples: four-bit register, D-latch, four-bit full adder, D flip-flop, J-K flip-flop, and four-bit multiplexer.
More complex designs: excess-3 BCD code converter, traffic light controller.
FPLD's: justification and examples.
ALTERA MAX+PLUS II
ALTERA 7000 PLD family
ALTERA examples (VHDL, AHLD, Graphic Editor)

TECHNICAL INFO

ASSIGNMENTS: