Today Controller Area Network (CAN) provides a modern infrastructure for automotive applications. It is a serial line architecture where bits can be dominant (representing a logical 0) and recessive (representing a logical 1). Medium access in CAN is based on the bit-wise arbitration schema, also called CSMA/BA (Carrier Sense Multiple Access with Bitwise Arbitration), where possible collisions are resolved by comparing sent and received bits on their type (dominant/recessive). In this talk we present a timed automata model of the CSMA/BA as it is used in CAN, his implementation in UPPAAL and then we discuss some properties of this model. We also refer to the problem of estimating upper delay bounds of CAN messages.

Biography

Dr. Dario Kresic is a postdoc at the University of Zagreb, Croatia. He received a Ph.D. degree in Computer Science from the University of Erlangen-Nuremberg, Germany (advisor: Ulrich Herzog), where he worked on verification techniques for real-time communication protocols. To pursue his research he received a Ph.D. fellowship by the German Research Foundation. He also worked at Siemens AG in Munich, Germany, in the area of interoperability for object-oriented distributed systems. His current research interests include intra-vehicular communication protocols and time modelling.

Today Controller Area Network (CAN) provides a modern infrastructure for automotive applications. It is a serial line architecture where bits can be dominant (representing a logical 0) and recessive (representing a logical 1). Medium access in CAN is based on the bit-wise arbitration schema, also called CSMA/BA (Carrier Sense Multiple Access with Bitwise Arbitration), where possible collisions are resolved by comparing sent and received bits on their type (dominant/recessive). In this talk we present a timed automata model of the CSMA/BA as it is used in CAN, his implementation in UPPAAL and then we discuss some properties of this model. We also refer to the problem of estimating upper delay bounds of CAN messages.

Biography

Dr. Dario Kresic is a postdoc at the University of Zagreb, Croatia. He received a Ph.D. degree in Computer Science from the University of Erlangen-Nuremberg, Germany (advisor: Ulrich Herzog), where he worked on verification techniques for real-time communication protocols. To pursue his research he received a Ph.D. fellowship by the German Research Foundation. He also worked at Siemens AG in Munich, Germany, in the area of interoperability for object-oriented distributed systems. His current research interests include intra-vehicular communication protocols and time modelling.