Power optimization in NanoCMOS must be observed in all levels of abstraction of the design flow and demands an important effort in optimization. As in NanoCMOS static power consumption is related to the amount of transistors, it is fundamental to change the design approach at physical level. It must be used an approach target to reduce the amount of transistors. The traditional standard cell flow don't really takes care of power minimization at physical level, because there is a limited number of logical functions in a cell library, as well a limited number of sizing versions. To really obtain an optimization at physical level, it is needed to allow the use of any possible logical function, by also using complex cells (Static CMOS complex gates . SCCG) that are not available in a cell library. To have a "freedom" in the logic design step, it is needed the use of an EDA set of tools to let the automatic design of any transistor network (even with a different number of P and N transistors). This approach can reduce the amount of transistors needed to implement a circuit, reducing the power consumption, mainly the leakage power. The talk presents some examples and comparisons between the standard cell approach and the network of transistors approach. The flexibility of the approach can also let the designers to define layout parameters to cope with problems like tolerance to transient effects, yield improvement, printability and DFM. The designer can also manage the sizing of transistors to reduce power consumption, without compromising the clock frequency. High temperatures can reduce the reliability, so it is also important to reduce power consumption to improve reliability. The talk shows a new approach to reduce the amount of transistors by using complex gates and a new set of EDA tools to generate any transistor network. Some results show an important reduction on power consumption, improving also circuit reliability.

Biography

Full Professor at Instituto de Informatica of the Universidade Federal do Rio Grande do Sul - UFRGS (professor since 1979). Electrical Engineering from the UFRGS, Porto Alegre, Brazil, in 1978. Ph.D. degree from the Polytechnic Institute of Grenoble (INPG), France, January 1983. Member of the Microelectronics Committee of National Council for Scientific and Technological Development (CNPq). Former member of the Computer Science Committee of National Council for Scientific and Technological Development (CNPq), for two terms. His primary research interests include Physical Design Automation and Methodologies, CAD tools, Circuits Tolerant to Radiation, VLSI Design Methodologies and Microelectronics Education. More than 350 hundred papers in journals and conferences proceedings. He is also author or co-author of several books. Invited speaker in several international conferences. Award as research of the year by the Science Foundation of Rio Grande do Sul, 2002. Silver Core award from IFIP. Research level 1A of the CNPq (Brazilian National Science Foundation). Head of several research projects. Past head of the Graduate Program in Microelectronics (2 terms) and of Computer Science Graduate Program at UFRGS (two terms). Professor and advisor at the Microelectronics and Computer Science Graduate Programs at UFRGS. General Chair or Program Chair of several conferences like the IFIP/IEEE VLSI-SoC, IEEE ISVLSI, IEEE LASCAS, Symposium on Integrated Circuits and Systems Design (SBCCI) and Congress of the Brazilian Microelectronics Society (SBMIcro). Past President of the Brazilian Computer Society and Past Vice-President of the Brazilian Microelectronics Society. IEEE CASS Chapter Rio Grande do Sul Chair (since 2007). Vice-president of IEEE Circuits and Systems representing R9, for two terms, from 2008 to 2011. Member of the Editorial Board of IEEE Design&Test. Member of the Steering Committee of the following conferences: IFIP/IEEE VLSI-SoC, ICECS, LASCAS, NEWCAS, IEEE CASS Summer School, IEEE ISVLSI, SBCCI, IBERCHIP. Senior member of IEEE.

Power optimization in NanoCMOS must be observed in all levels of abstraction of the design flow and demands an important effort in optimization. As in NanoCMOS statitc power consumption is related to the amount of transistors, it is fundamental to change the design approach at physical level. It must be used an approach target to reduce the amount of transistors. The traditional standard cell flow don't really takes care of power minimization at physical level, because there is a limited number of logical functions in a cell library, as well a limited number of sizing versions. To really obtain an optimization at physical level, it is needed to allow the use of any possible logical function, by also using complex cells (Static CMOS complex gates . SCCG) that are not available in a cell library. To have a "freedom" in the logic design step, it is needed the use of an EDA set of tools to let the automatic design of any transistor network (even with a different number of P and N transistors). This approach can reduce the amount of transistors needed to implement a circuit, reducing the power consumption, mainly the leakage power. The talk presents some examples and comparisons between the standard cell approach and the network of transistors approach. The flexibility of the approach can also let the designers to define layout parameters to cope with problems like tolerance to transient effects, yield improvement, printability and DFM. The designer can also manage the sizing of transistors to reduce power consumption, without compromising the clock frequency. High temperatures can reduce the reliability, so it is also important to reduce power consumption to improve reliability. The talk shows a new approach to reduce the amount of transistors by using complex gates and a new set of EDA tools to generate any transistor network. Some results show an important reduction on power consumption, improving also circuit reliability.

Biography

Full Professor at Instituto de Informatica of the Universidade Federal do Rio Grande do Sul - UFRGS (professor since 1979). Electrical Engineering from the UFRGS, Porto Alegre, Brazil, in 1978. Ph.D. degree from the Polytechnic Institute of Grenoble (INPG), France, January 1983. Member of the Microelectronics Committee of National Council for Scientific and Technological Development (CNPq). Former member of the Computer Science Committee of National Council for Scientific and Technological Development (CNPq), for two terms. His primary research interests include Physical Design Automation and Methodologies, CAD tools, Circuits Tolerant to Radiation, VLSI Design Methodologies and Microelectronics Education. More than 350 hundred papers in journals and conferences proceedings. He is also author or co-author of several books. Invited speaker in several international conferences. Award as research of the year by the Science Foundation of Rio Grande do Sul, 2002. Silver Core award from IFIP. Research level 1A of the CNPq (Brazilian National Science Foundation). Head of several research projects. Past head of the Graduate Program in Microelectronics (2 terms) and of Computer Science Graduate Program at UFRGS (two terms). Professor and advisor at the Microelectronics and Computer Science Graduate Programs at UFRGS. General Chair or Program Chair of several conferences like the IFIP/IEEE VLSI-SoC, IEEE ISVLSI, IEEE LASCAS, Symposium on Integrated Circuits and Systems Design (SBCCI) and Congress of the Brazilian Microelectronics Society (SBMIcro). Past President of the Brazilian Computer Society and Past Vice-President of the Brazilian Microelectronics Society. IEEE CASS Chapter Rio Grande do Sul Chair (since 2007). Vice-president of IEEE Circuits and Systems representing R9, for two terms, from 2008 to 2011. Member of the Editorial Board of IEEE Design&Test. Member of the Steering Committee of the following conferences: IFIP/IEEE VLSI-SoC, ICECS, LASCAS, NEWCAS, IEEE CASS Summer School, IEEE ISVLSI, SBCCI, IBERCHIP. Senior member of IEEE.